The invention relates generally to electrical device packaging and more particularly to packaging of electrical devices requiring energy transmission to and/or from device active areas.
As the need for smaller, lighter, portable and/or mobile equipment increases in applications such as medical imaging, consumer electronics, and communication devices, the need for high density device and system level packaging likewise increases. High density packages would be most beneficial if adapted for interconnecting hundreds of input and output pads and providing an unobstructed path for transmission and/or absorption of energy directed to and/or from the active area of a packaged device.
For example, ultrasound imaging equipment uses active areas of electrical devices to transmit and receive hundreds of acoustic signals which can be used to create images of patient anatomy. The active areas of these devices must be substantially free of material that would attenuate or distort the signals. Accordingly, ideal packaging technology would be capable of interconnecting high pin count acoustic devices with fine pitched (less than 0.2 millimeter, for example) input/output pads and providing an open window over the active area of each packaged device. Preferably, such an open window would offer protection from damage to the device active area during the packaging process.
Cole et al., U.S. Pat. No. 5,527,741, issued Jun. 18, 1996, describes a method for fabricating a circuit module by forming a flexible interconnect layer of multiple layers of metallized polymer film, attaching a circuit chip to the film with an adhesive, forming vias through the flexible interconnect layer, and applying metallization to couple chip pads through the vias. Such flex-based packaging has been useful for high pin count devices with fine pitch but has resulted in embodiments wherein the entire active area of the device is covered by the flexible interconnect layer. Thus such packaging has been limited with respect to optical or acoustic sensors that cannot operate efficiently when covered by material which attenuates or distorts energy transmission.
As described in Kornrumpf et al., U.S. Pat. No. 5,355,102, issued Oct. 11, 1994, ablating dielectric material over the center of a device may adversely affect the device. To protect microwave devices, Kornrumpf et al. recommended placing a small piece of polytetrafluoroethylene or other non-laser ablatable material on top of the active area of the device to cover the region from which the dielectric is to be removed after completion of the high density interconnect fabrication process, and, after such fabrication, cutting the dielectric layers and removing the piece of polytetrafluoroethylene.
It would desirable to provide a fabrication method for an electronic package with an open window over the device active area and with high pin count interconnections.
Briefly, in accordance with one embodiment of the present invention, a method for forming an interconnect structure comprises: applying a first metallization pattern on a dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; using an adhesive to attach a protective cover sheet over the first metallization pattern and the dielectric layer; aligning at least one mask opening with the at least one etch stop opening; removing a first portion of the adhesive through the at least one mask opening; removing the cover sheet; using a second portion of the adhesive to attach at least one electrical device such that an active area of the at least one electrical device is aligned with the etch stop perimeter; and curing the second portion of the adhesive.
In accordance with another embodiment of the present invention, an interconnection structure comprises: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter.
In accordance with another embodiment of the present invention, a probe comprises: at least one energy-oriented probe electrical device including an active area and at least two device pads; a dielectric layer having an opening aligned with the active area of the electrical device; an adhesive coupling the dielectric layer and a non-active area of the device; at least two vias extending through the dielectric layer to the at least two device pads; and a metallization pattern extending into the at least two vias to contact the at least two device pads to couple the electrical device pads to probe equipment.
In accordance with another embodiment of the present invention, a method for fabricating an interconnection structure comprises: applying an adhesive over a dielectric layer; curing a first portion of the adhesive through at least one mask opening; using a second portion of the adhesive to attach at least one electrical device such that an active area of the at least one electrical device is aligned with the first portion of the adhesive; and curing the second portion of the adhesive.
In accordance with another embodiment of the present invention, an interconnection structure comprises: a dielectric layer; a first portion of cured adhesive; a second portion of cured adhesive; at least one electrical device being attached to the dielectric layer by the second portion of cured adhesive such that an active area of the at least one electrical device is aligned with the at least one predetermined area defined by the first portion of cured adhesive, the first portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.